THE DEFECT-SENSITIVITY EFFECT OF MEMORY CHIPS

被引：11

作者：

STAPPER, CH

机构：

[1] IBM Development Lab, Essex Junction,, VT, USA, IBM Development Lab, Essex Junction, VT, USA

来源：

关键词：

D O I：

10.1109/JSSC.1986.1052498

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

DATA STORAGE, SEMICONDUCTOR

引用

页码：193 / 198

页数：6

共 14 条

[1]

DENNARD RA, COMMUNICATION

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FERRISPRABHU, AV .

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HEMMERT, RS .

[5]

HEMMERT RS, COMMUNICATION

[6]

MOORE GE, 1970, ELECTRONICS, V43, P126

[7] MULTIPLE WORD-BIT LINE REDUNDANCY FOR SEMICONDUCTOR MEMORIES [J].

SCHUSTER, SE .

[8]

SEEDS RB, 1967, 1967 INT EL DEV M KE, P12

[9]

SEEDS RB, 1967, 1967 IEEE INT CONV 6, P60

STAPPER, CH .